A major driving force in electronics is the miniaturisation of the transistor – a device that essentially acts like an electrically controlled tap for electrons. In a transistor, the electrical current flowing from source to drain is controlled electrostatically by a third electrode called a ‘gate’. One avenue to ultra-small transistors is to make them using self-assembled semiconductor nanowires, but a challenge is how to make gates that work effectively for such tiny transistors. The most effective gates wrap entirely around the nanowire, they’re called ‘wrap-gates’, but are not easy to make for a nanowire sitting horizontally on a chip.

In 2012, the international team (led by A/Prof Adam Micolich at UNSW and Prof Lars Samuelson at Lund) reported a major step in overcoming this hurdle by successfully taking semiconductor nanowires grown vertically from the substrate, depositing gate metal on the outside and then ‘knocking them over’ to sit horizontally on the substrate before completing the device fabrication (see Storm et al., Nano Letters 12, 1 (2012)).

The team has now developed a method for making a larger number of independently controllable wrap-gates on a single horizontal nanowire – a key step towards logic devices and more complex integrated circuits (see Burke et al., Nano Letters 15, 2836 (2015)). The most significant aspect of the work is that this new process reveals a major scalability advantage for horizontal nanowire transistors relative to their vertically-oriented cousins, which have seen more interest from industry to date. In the vertical orientation, each extra gate requires the repetition of a complex set of fabrication steps which add cost and reduce yield. In the horizontal orientation, additional gates can be added without this cost.

The research has implications for approaches to making larger scale circuits from nanowire transistors, particularly towards the vision of having electronics built using 3D networks of nanowire transistors to maximise the density of transistors per unit of chip area.